SoC DFX Timing Engineer

This role is focused on full-chip test mode timing signoff and SDC quality checks to ensure robust DFT implementation and timing closure. The engineer will support cross-die STA activities, enhance STA automation flows, and work closely with Front-End and Physical Design teams to drive synthesis optimization, timing validation, and successful full-chip timing signoff. We are looking for a collaborative team player with strong Verilog RTL design knowledge and experience, while exposure to synthesis, scan/BIST, multi-power timing signoff, and STA methodologies would be highly advantageous. Responsibilities include (but are not limited to): • Cutting-edge test strategies study and implementation. • DFT sdc development and maintenance. • Support special timing check and multi-voltage timing check. • Timing sign-off automation flow enhancement. • Co-work with Front End design team for synthesis optimization and sdc quality check. • Co-work with Physical design team for full chip smooth timing signoff.

• Master’s degree with 1 year or Bachelor with 3 years’ experience at least. • Minimum 5 years of experience in STA, timing signoff, synthesis, RTL design, DFT timing analysis, or physical design environments. • Solid background on process, device or ASIC design. • Strong technical background in Verilog coding. • Experience in Design Compiler, Fusion Compiler and Primetime EDA tools will be a plus. • Good knowledge on DFT Scan/BIST will be a strong plus. • Good knowledge on CTS and ICC physical design flow will be a strong plus. • Proven knowledge and expertise on two or more fields of SCAN, MBIST, RTL design, STA and DV. • Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus. • Good communication skills (both English and Mandarin) and self-driven, willing to learn/share.